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Watchdog: not able to suspend Linux on at91sam9263
Hello,
If I enable the watchdog in the bootstrap, then I can’t suspend linux because there’s no way to kick the watchdog if I do that. Furthermore, I can’t disable the watchdog as it can be done with the at91rm9200. I have tried to configure the watchdog so that it disables itself when the processor is in idle state, but this way the watchdog never resets the processor while working in linux.
What can I do? Thanks in advance
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Hi, Iam using at91sam9263 with bootstrap and uboot in dataflash and linux kernel and rootfs in nand flash. whenever i load the driver at91sam9_wdt.ko it says that watchdog is already initialised. I came to know that in bootstrap is disabled by default. at91sam9263ek.c file hw_init /* Disable watchdog */ writel(AT91C_WDTC_WDRSTT,AT91C_BASE_WDTC + WDTC_WDCR); i commented this line so that i can enable the watchdog at the later time. but by default watchdog is enabled and resets the processor every 16 seconds. also we can write to the watchdog mode register only once. how to disable the watchdog until kernel boots up ...I'm trying to have the watchdog disabled when going to standby or suspend-to-mem mode in Linux so that it doesn't restart the system. I'm using the at91sam9g45ekes board. Is there any way of doing this? I added the flag AT91_WDT_WDIDLEHLT to the driver hoping that it would halt the watchdog but in reality what it's doing is pretty much disabling the watchdog all the time. I opened the device but never kicked the watchdog and got the "I will reset your machine !" message but nothing happened. If I go to standby the system keeps running but if i try suspend-to-mem ...ive been trying to get this to work. i have at91sam9263 with bootstrap and uboot in dataflash and linux kernel and rootfs in nand. i have no idea how to get it to work. bootup says at91sam9_wdt: invalid timeout (must be between 1 and 16) i studied this and found out that watchdog in bootstrap is disabled by default. at91sam9263ek.c file hw_init /* Disable watchdog */ writel(AT91C_WDTC_WDRSTT,AT91C_BASE_WDTC + WDTC_WDCR); i changed this to writel(0xFFF | (0xFFF ltlt 16) | AT91C_WDTC_WDRSTEN | AT91C_WDTC_WDDBGHLT | AT91_WDTC_WDIDLEHLT,AT91C_BASE_WDTC + WDTC_WDCR); now the watchdog seems to be functioning because the device resets itself every 16 ...Hi I'm having more problems I expected enabling the watchdog in my developper kit at91sam9g20-ek board. Using menuconfig I've compiled the watchdog driver correctly, but when booting the linux kernel, I obtain this: AT91SAM9 Watchdog: sorry, watchdog is disabled at91_wdt: probe of at91_wdt failed with error -5 Viewing the watchdog driver code I guess my problem is my watchdog is not enabled, it is? So, how can I do to enable the watchdog when booting? Another question: after loading the watchdog driver, I must refresh continuously the driver to avoid reset? In other words: the watchog is started when is enabled? Thanks you in advance Regards, ardosterHello, In all of my past experiences with a watchdog timer, the behavioral model has been the following: * Configure the watchdog to certain timeout period. * Call a function to reset the watchdog more frequently than the timeout periond. * If the watchdog is not reset before the timeout period, the processor is reset. I would like to use the watchdog on my LM3S8962. But when I look at the Stellarisware watchdog example, I see that the ampquot;resettingampquot; of the watchdog timer is done in an ISR. This does not seem like a good design ...Hi, I am using the AT91SAM9263 based board and i have Linux 2.6.20 up and running. but i dont find the dirver for watchdog module with this BSP. Has anybody ported the watchdog driver for this microcontroller. Kindly help. its urgent. thanks in advance with regards Shashi shashikumar@aspirecom.netHi all, i'm quite new with AT91. Hope can get helps from you all... Currently I'm using AT91SAM7S256 for my project... and planning to use the watchdog to reset the system when the software hanged. I had went through the database search, and did the same things.. but doesnt working.. As mentioned in datasheet, the watchdog is using slow clock at 32.768kHz. Would like to double confirm whether I need to set any clocks in order to get the slow clock run at 32.768kHz as needed for watchdog. If yes, what is the sequence to configure the clock properly? Below is my code. Does the watchdog ...Hi, i'm working on a AT91SAM7X-EK development board, and i'm trying to figure out if the normal at91 watchdog behavior can be changed or workarounded because: "The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset resets it. Writing the WDT_MR register reloads the timer with the newly programmed mode parameters." due to this feature, if i disable watchdog on start up, i'm not able to turn in on anymore until the next reset. What i want to do is disable watchdog on startup, and then turn it on later (on a custom received can message). ...New here, but not my first rodeo.. I am working on a rather complex program that uses the Watchdog timer for its obvious uses. Timer0 is also used to generate interrupts for the system clock. I need to be able to disable the Watchdog via a command from another system so that both systems can be reburned in the field. The watchdog is under software enable via the swdten bit (and this is working). When I disable the watchdog, the interrupts from timer0 also stop. I have even added code to enable timer0 immediately after resetting the swdten bit, to ...Please suggest a method to test the External Watchdog during each Boot-up of the code. The Problems I am facing are 1) Self Testing Watchdog if proper, gives Reset to the processor. 2) Using no.1, I am not able to differentiate the Power-On reset and Watchdog reset. Some site suggest that one can use the Sleep Mode for testing the Watchdog. Anyone tried this? Thank you in Advance.I'm using the AT91SAM7SE512. The watchdog is running with a time period of two seconds. In the initialisation code I can detect a watchdog reset (together with all the other types). My question is this:- if a watchdog reset happens is there anyway of knowing where the processor was just before the watchdog kicked in? Of course, I've read the datasheet but there is no mention of a separate register etc. that holds the program counter nor any other information that I can find. Any thoughts? PeteGreetings. I'm working with the RCM5700 module. I need to use the hardware watchdog timer. Supposedly, the watchdog is always enabled, but I never use the hitwd function to restart it, and my device never restarted. Now. I use the Enable_HW_WDT function to enable the watchdog, but my hardware never restarted. Is there anything I forgot to configure? Please help me. ThanksIm using a m1284. START Watchdog is working but once startet, the watchdog cant be stopped. I tried STOP Watchdog.... The sequence: Clear_Watchdog: 'this sub toggles the watchdog into and out of interrupt / reset mode 'this ensures that no matter what mode the watchdog might have been in previously... 'it will be turned off completely CLI 'disable global interrupts WDR 'reset watchdog timer IN R16, MCUSR 'get MCUSR ANDI R16, $F7 'clear the watchdog reset bit in the status reg !OUT MCUSR, R16 'store MCUSR LDS R16, WDTCSR 'get current watchdog setting LDI R17, $58 'load int/res mode value ...Hello, I'm using the 9263 watchdog and I have seen that when used with the NOWAYOUT option, the watchdog will not be refreshed by the driver even before /dev/watchdog is opened. http://www.mjmwired.net/kernel/Documentation/watchdog/watchdog-api.txt seems to imply that NOWAYOUT should only apply after /dev/watchdog has been opened at least once. Anyone know if this behaviour is intentional? Or is it a bug? It is currently a headache for me because my systems may be slow to start up if the flash is too fragmented and the WD may be triggered simply because the userspace daemon takes too long to start. Regards DavidHello everyone, I would like to use the watchdog as a watchdog, instead of as a timer. Meaning I would like to set the watchdog timer to a certain time and if I do not disable it before the time expires, it should reset the MCU. Does anyone have an example code for this? GreetingsI have COP enabled. If I put the program into a loop without a watchdog reset, the processor resets as expected. But the SRS register alomost always is clear. Sometimes the PIN bit is set, sometimes the COP bit is set, sometimes POR bit is set. Most of the time the register is clear. If I debug, and cause a watchdog timeout, the SRS_COP is set. I just power up the project and I got a SRS_POR. Then I reset the processor by the reset pin and got a SPS_POR.Hi. I would like to reset my ATmega48 via software/watchdog, so I decide to use the wdt.h library from the avr-gcc toolchain. You can access a simple code example by downloading the "main.c" attachment. My problem is, that the processor goes into an endless loop of Watchdog resets and I have no idea how to solve this state. I tried to use wdt_disable() and wdt_reset() but it did not work. Info about the project: ATmega48 RS232/USB devel boardHi all. First of all, we are using a LM3S9B90 Rev. C3 and StellarisWare rev. 6852. Our application is using a watchdog, which is working fine. However, whenever I enter DFU mode (using the USB capable boot loader), this is done by calling USBDDFUUpdateBegin(), and the device enters DFU mode without being reset. This causes an issue, as the watchdog is not disabled, and will, when it counts down, reset the MCU. Once enabled, there is no possibility to disable the watchdog, and issuing WatchdogResetDisable(WATCHDOG0_BASE) causes an error. How can we prevent the watchdog from resetting the MCU while in ...Hi, all The watchdog puzzled me for several days, why the watchdog doesn't reset after following initialization void watchdog_init(void) { AT91F_WDTC_CfgPMC(); AT91C_BASE_WDTC-gtWDTC_WDMR = AT91C_WDTC_WDV|AT91C_WDTC_WDD|AT91C_WDTC_WDRSTEN|AT91C_WDTC_WDIDLEHLT||AT91C_WDTC_WDDBGHLT; } but if I change "WDT_MR_Val EQU 0x00008000" to "0x3FFF2FFF" in "SAM.s", the watchdog is ok... I notice "The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset resets it. Writing the WDT_MR register reloads the timer with the newly programmed mode parameters." but i'm not very clear about it, if WDT_MR can be written only once, what does reloads means??? hlps, thanksHello, 1)I have coded PIC16F676 for one system. Before using WatchDog, the ADC code in my program works appropriately. I am taking analog signal on Port A - 0 pin (AN0). But after enabling Watchdog through Configuration bits, ADC working is erratic. Code structure is below: This is with watchdog CONFIG bit enabled 1. Init registers,ports etc 2. Call ADC routine 3. ----- 2)If I disable the Watchdog CONFIG bit and then if I assign prescalar to Watchdog through the code given in datasheet(initially for 30 secs I am using prescalar for Timer), then Watchdog is not active at all. I ...