Using watchdog as a watchdog
I would like to use the watchdog as a watchdog, instead of as a timer. Meaning I would like to set the watchdog timer to a certain time and if I do not disable it before the time expires, it should reset the MCU. Does anyone have an example code for this?
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Hello, In all of my past experiences with a watchdog timer, the behavioral model has been the following: * Configure the watchdog to certain timeout period. * Call a function to reset the watchdog more frequently than the timeout periond. * If the watchdog is not reset before the timeout period, the processor is reset. I would like to use the watchdog on my LM3S8962. But when I look at the Stellarisware watchdog example, I see that the ampquot;resettingampquot; of the watchdog timer is done in an ISR. This does not seem like a good design ...Compiling an existing PIC32 project using the v2.00 C compiler produces a continual watchdog reset. This problem does not appear using the previous v1.12 compiler. Changing the watchdog postscaler value (up to 1048 seconds) has no effect. The watchdog reset occurs almost immediately after startup, definitely not enough time for the timer to expire. Disabling the watchdog allows the code to run as expected. There was a change to the startup code in v2.00, but I am not using any custom startup code to my knowledge. Could there be a problem with the timer used by the watchdog not being ...Hi all, I am developing an application for Elevator Control, and I want a reliable WatchDog timer, I had a bad experiance when I was working with PIC mircocontroller that on power up the PIC didnt make self reset and also the watchdog timer didnt reset the PIC even the WatchDog was Enabled by Fuse(not by the software), my current design is using ATMEGA8, I am afraid this problem may occar with the ATMEGA8, so I made a design for a hardware WatchDog timer, but this will take more area on the PCB, so I need your advice, can I ...Im using a m1284. START Watchdog is working but once startet, the watchdog cant be stopped. I tried STOP Watchdog.... The sequence: Clear_Watchdog: 'this sub toggles the watchdog into and out of interrupt / reset mode 'this ensures that no matter what mode the watchdog might have been in previously... 'it will be turned off completely CLI 'disable global interrupts WDR 'reset watchdog timer IN R16, MCUSR 'get MCUSR ANDI R16, $F7 'clear the watchdog reset bit in the status reg !OUT MCUSR, R16 'store MCUSR LDS R16, WDTCSR 'get current watchdog setting LDI R17, $58 'load int/res mode value ...I'm using the AT91SAM7SE512. The watchdog is running with a time period of two seconds. In the initialisation code I can detect a watchdog reset (together with all the other types). My question is this:- if a watchdog reset happens is there anyway of knowing where the processor was just before the watchdog kicked in? Of course, I've read the datasheet but there is no mention of a separate register etc. that holds the program counter nor any other information that I can find. Any thoughts? PeteHi all, i'm quite new with AT91. Hope can get helps from you all... Currently I'm using AT91SAM7S256 for my project... and planning to use the watchdog to reset the system when the software hanged. I had went through the database search, and did the same things.. but doesnt working.. As mentioned in datasheet, the watchdog is using slow clock at 32.768kHz. Would like to double confirm whether I need to set any clocks in order to get the slow clock run at 32.768kHz as needed for watchdog. If yes, what is the sequence to configure the clock properly? Below is my code. Does the watchdog ...Hello, 1)I have coded PIC16F676 for one system. Before using WatchDog, the ADC code in my program works appropriately. I am taking analog signal on Port A - 0 pin (AN0). But after enabling Watchdog through Configuration bits, ADC working is erratic. Code structure is below: This is with watchdog CONFIG bit enabled 1. Init registers,ports etc 2. Call ADC routine 3. ----- 2)If I disable the Watchdog CONFIG bit and then if I assign prescalar to Watchdog through the code given in datasheet(initially for 30 secs I am using prescalar for Timer), then Watchdog is not active at all. I ...I run my FEZ Cobra with 7" display amp watchdog timer set to 5 sec. One of my customers reports the display freezes in some situations. FEZ Cobra however is not reset by the watchdog timer? Is it possible FEZ completely locks up and even the watchdog timer is not triggered in such case? Any of you guys seen this before? TIA JosHi, i'm working on a AT91SAM7X-EK development board, and i'm trying to figure out if the normal at91 watchdog behavior can be changed or workarounded because: "The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset resets it. Writing the WDT_MR register reloads the timer with the newly programmed mode parameters." due to this feature, if i disable watchdog on start up, i'm not able to turn in on anymore until the next reset. What i want to do is disable watchdog on startup, and then turn it on later (on a custom received can message). ...Hello, If I enable the watchdog in the bootstrap, then I can't suspend linux because there's no way to kick the watchdog if I do that. Furthermore, I can't disable the watchdog as it can be done with the at91rm9200. I have tried to configure the watchdog so that it disables itself when the processor is in idle state, but this way the watchdog never resets the processor while working in linux. What can I do? Thanks in advanceHi I'm having more problems I expected enabling the watchdog in my developper kit at91sam9g20-ek board. Using menuconfig I've compiled the watchdog driver correctly, but when booting the linux kernel, I obtain this: AT91SAM9 Watchdog: sorry, watchdog is disabled at91_wdt: probe of at91_wdt failed with error -5 Viewing the watchdog driver code I guess my problem is my watchdog is not enabled, it is? So, how can I do to enable the watchdog when booting? Another question: after loading the watchdog driver, I must refresh continuously the driver to avoid reset? In other words: the watchog is started when is enabled? Thanks you in advance Regards, ardosterDear sir, I am using ADUC842 for my design. I want to set watchdog timer of 2 sec for any errorneous condition. In my main function, i have enabled all interrupts already... I need to configure watchdog timer. But before that i should disable all the interrupts,set the watchdog timer and again enable the interrupts. since i have enabled all interrupts,i cant configure watchdog timer in the main function. where should i configure the watchdog timer ? pls help. Regards, Mayuri GNew here, but not my first rodeo.. I am working on a rather complex program that uses the Watchdog timer for its obvious uses. Timer0 is also used to generate interrupts for the system clock. I need to be able to disable the Watchdog via a command from another system so that both systems can be reburned in the field. The watchdog is under software enable via the swdten bit (and this is working). When I disable the watchdog, the interrupts from timer0 also stop. I have even added code to enable timer0 immediately after resetting the swdten bit, to ...I am working on a program for an 18LF45K22 using the CCS compiler. There is one section of the code where I go into an infinite loop with a while(1) and I want the watchdog to time out and reset the CPU. Immedaitely before the code hits the while(1) I disable global interrupts. For some reason the watchdog will never time out and reset unless I take out the disable global interrupts. The watchdog works just as expected if the global interrupts are enabled when it hits the while(1). I could find nothing in the documentation to indicate why the ...Hey guys (and maybe gals), I was wondering if anyone knows whether the watchdog timer always occurs before a reset? (Obviously if the registers are set to do both) on the mega168. The only reason I ask is that I have had some unexpected events although the watchdog ISR hasn't executed, and I can only assume the watchdog ISR was never called as the reset occurred while in an interrupt. Is this correct as I cant find any information stating this in the manual? Thanks in advance.Reading over the watchdog timer section of the UM for the LPC17xx family it states - "Once the WDEN and/or WDRESET bits are set they can not be cleared by software. Both flags are cleared by an external reset or a Watchdog timer underflow. [page 568 - CH28 section 4.1]". Since instructions are not executed during Sleep - how do you feed / kick / service the watchdog? I thought that by using the PCLK this would be an issue since the PCLK should not be running during Sleep, consequently not decrementing the counter but this is not ...Please suggest a method to test the External Watchdog during each Boot-up of the code. The Problems I am facing are 1) Self Testing Watchdog if proper, gives Reset to the processor. 2) Using no.1, I am not able to differentiate the Power-On reset and Watchdog reset. Some site suggest that one can use the Sleep Mode for testing the Watchdog. Anyone tried this? Thank you in Advance.The WDTCSR is the WatchDog Timer Control Register. Each of it's eight named bits means something different. WDE is the WatchDog Enable bit, and WDP0, WDP1, WDP2 and WDP3 are the WatchDog Prescale bits. They are used to select (effectively) the time-out on the WatchDog. The combination of WDP1 and WDP0 indicate that the timeout should be about half a second.Hi all. First of all, we are using a LM3S9B90 Rev. C3 and StellarisWare rev. 6852. Our application is using a watchdog, which is working fine. However, whenever I enter DFU mode (using the USB capable boot loader), this is done by calling USBDDFUUpdateBegin(), and the device enters DFU mode without being reset. This causes an issue, as the watchdog is not disabled, and will, when it counts down, reset the MCU. Once enabled, there is no possibility to disable the watchdog, and issuing WatchdogResetDisable(WATCHDOG0_BASE) causes an error. How can we prevent the watchdog from resetting the MCU while in ...Two undesirable effects of using a watchdog timer: 1. When implementing the Fez watchdog timer, I've noticed that when monitoring the serial port, I get a mess of seemingly random characters transmitted from the Domino to the PC just prior to reboot. 2. Also, having watched and repeated this behavior a number of times, I also note, curiously enough, that the Domino once rebooted by the watchdog timer now redirects debugging information out to the serial port instead of the USB port, which it appears to lock-out. (The PC no longer sees the USB port after a watchdog reset.) As I am interfacing ...
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