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Timer overflow & RC compare bug
I believe I have found a silicon bug in AT91SAM7SE512 (although it’s probably present in other variants).
I have timer 0 set up to free-run, and cause an interrupt on both overflow amp RC compare.
My ISR reads TC_SR to clear the interrupt condition so the next event (either overflow or RC compare) will trigger a new interrupt.
If both overflow amp RC compare occur at the same time, the ISR gets called once, and by reading the SR it can determine that it needs to process both events.
If overflow amp RC compare occur separated by a long time, then two interrupts are triggered.
If overflow and RC compare occur close to each other, then the following can occur:
- Timer overflow occurs
- ISR called
- ISR reads SR, at exactly the same time as RC compare occurs
- ISR processes overflow, SR is set to indicate that RC compare as occurred.
- AIC does NOT trigger another interruptSo therefore interrupts stop. SR indicates that another interrupt should be triggered, but this doesn’t happen until SR is read (manually).
It doesn’t seem to matter whether the first event is overflow or RC compare.
It’s quite hard to recreate, so I think the timing is critical.
Is this a known issue with the timers?. I have a sample project (Eclipse, GCC) that demo’s it (albeit for my hardware). Where should I send it?
Anybody else seen this?
Is there a workaround (apart from using two synchronised timers!)
Thanks,
Chris.
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