Prop II question : Serial Chip-To-Chip Communication
The new Prop II spec
Each cog now also features high-speed serial transfer and receive hardware for chip-to-chip communication. The hardware requires three I/O pins (SO, SI, CLK). Opcodes are SNDSER RCVSER SETSER "]
but this seems to exclude both Standard SPI and QuadSPI support ?
That’s a large blind spot – standard SPI receives as it sends, and QuadSPI is the emerging standard for large FLASH memory.
So near, and yet so far…
SPI does not appear anywhere in the DOCs … Do parallax imagine Prop IIs will ONLY talk to other Prop IIs ?
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