Archives
-
MCF54450 V4e SRAM performance
Hello all.
I’m working on a rather software-intensive application (video encoder) at the moment, and am trying everything possible to optimise my code. I have discovered that the on-board 32kB SRAM does not seem to be as fast as it should be:
After writing some simple data-copying benchmarks, I have the following results:
DDR to DDR copy = 40.8 MB/s (copyback mode)
DDR to DDR copy = 79.2 MB/s (write-through mode)
SRAM to SRAM copy = 129.6 MB/s
Cache to cache copy = 399.2 MB/s(Platform is MCF54450 at 240MHz with mobile-DDR external memory. Copies run with simple MOVEM loops – not DMA)
Now, the datasheet says the SRAM is single-cycle and on the processor’s local high-speed bus. Should this not therefore give a bandwidth of 960MB/s, or copy performance of 480MB/s for 32-bit wide memory? I’m getting this sort of speed from the cache, but the SRAM seems far too slow. If the SRAM is this slow, what’s the point of it? Code or data structures will always be faster in cached external memory.
I have played about with the RAMBAR settings, and am accessing the SRAM properly – not through the backdoor!
Thanks for any advice!
Steve.
PS. If anyone’s interested in my benchmarking routines, let me know and I’ll post them.
Solved! Go to Solution.
Related Forum Messages
- SRAM vs FLASH
- Running executable from external SRAM
- Instruction Cache, MCF523x processor, CodeWarriors…
- Testing the integrity of SRAM
- Running boot code by embedded sram.
- Copy External Flash to External Ram, then Execute
- External Memory Support
- Optimisation of memory configuration on LPC4350 (Cortex-M4/M0 Dual Core)
- About the usage of SRAM
- MCF5329 expected SDRAM Memory Bandwidth
- Microprocessor controlling SRAM through an FPGA
- Is SAM BA is copy itself in flash or sram?
- Memory Mapping 1Mb SRAM to LM3S3748
- 2 FEZ 1 SRAM
- VGA TFT with ‘DA210 and external SRAM
- MCBSTM32F400 external ram
- Is all SRAM created equal?
- Atmega128 external SRAM
- SRAM vs Cache
- External memory SRAM
Hi, I would like to store data in a 16kByte SRAM. When the memory of the SRAM has for example reached 10kByte it must send it to a FLASH sd- memorycard of 1GB. Meanwhile the SRAM is still storing new data in the SRAM cells. Does someone knows if reading and writing simultaneously in SRAM is possible ? And is there a maximum write/erase cycle for SRAM? (not mentionned in ATmega datasheet) Thank you !I have an STM32 dev board with some external SRAM. I would like to execute my code from that external SRAM, but my processor only supports booting from the Flash, internal SRAM or System memory (a part of the internal SRAM). What is the easiest way to run code from an external SRAM? Notes: I load code with OpenOCD through JTAG, and I use GDB.Hello! Please Help! I have my own prototype design up and working. Now I'm trying to get the cache enabled to increase performance. For this processor, the cache is 8KBytes. The processor also has a 64KByte internal SRAM (non-cachable). Code is executed from an external Flash memory chip (8MBytes Flash on CS0 in x16 configuration). The cache for this processor can either be instruction, data, or split 50%/50% instruction and data. For my application, instruction only will provide best performance increase. There are only three relevant registers ...I am testing a board that has external SRAM. Apparently the SRAM is relatively sensitive to the soldering heat from the manufacturing process, and so careful testing must be done to check integrity of SRAM for newly manufactured boards. What is the best (bare-metal) way to test SRAM? I have a driver that initialises the SRAM for read/write access. My first thought is to run tests such as: 1) Set all bits in SRAM to 1, and check that the SRAM was properly written. 2) Write the digits of Pi in SRAM, and check that the write was done properly. ...Hello everybody. I modify a flash.sct file in SAM3U-EK example code for running boot code that is stored in embedded flash memory(128KB) by sram(32KB) Base concept is 'copy the codes from Flash to SRAM and jump to the SRAM and excute it' Before Code:Here is the problem. Code is located in 0x1000_0000 (Chip select 0), it is an external flash. The program can boot off there and run. I need to be able to write to the flash. I tried appending the keyword "__ramfunc" and it just jumps to the area 0x4 (Not sure what error that is). I am a computer scientist, with no formal computer engineering training. And i am the sole person working on this project. So i am a bit out of my league. I have a flash driver written, and i am able to get the Manufacturer ID and Device ...I am using 18F97J60 w/ MPLAB-IDE v8.15a amp RealICE (in Debug mode). I am attempting to enable external SRAM support and have properly modified the .lkr script to support it. I am able to successfully read/write to the SRAM (using executable code) which starts @ 0x20000, however, I cannot inspect it's contents in a watch window. The watch window paints a green 'P' in the left column (which I assumes means PGM memory ... or something) I also cannot inspect this ext SRAM contents in the program memory window. Can MPLAB paint the ext ...Hello everyone, We're about to begin a project with NXP's LPC4350 chip, which features the following memory configuration: - 128kB Local SRAM - 72kB Local SRAM - SPIFI - 32kB AHB SRAM - 16kB AHB SRAM - External Memory Controller (SRAM, SDRAM) The LPC4350 features a dual-core M4 and M0 clocked at up to 204MHz. Instinctively we wish to use the 128 and 72kB memory banks for the M4 Data and Instruction buses, as these are in the accessible memory range, whilst AHB elements run only on the system bus. However, we wish to offload MDK Ethernet functionality to the M0 and, with a little ...Hi Experts, On the LPC1668, there are totally 64kB of SRAM, 32kB of main SRAM, and two 16kB AHB SRAM. Is it possible to use the 32kB main SRAM as heap, and 8kB on one of the 16kB AHB SRAM as stack? If yes, how can we do that? Thanks very much! Regards, Jessamine240MHz MCF5329 on our own board with 32-bit SDRAM and FLASH on the FlexBus. The LCD is in use, but disabled for these tests. I'm testing memory copy and write speed and maxing at 80MB/s. I'd hope for higher with 80MHz 32-bit wide SDRAM. The clocks are running at the right speed (240MHz/80MHz). The Cache is on, in Writethrough mode (writeback is a lot slower) and the cache write queue is on (also makes a big difference). The Crossbar is set up to allow bursting. I've got interrupts and all DMA disabled during these ...I have an ARM Cortex 3M (reference manual here) connected through the FSMC (Flexible Static Memory Controller) to a Spartan 6 FPGA. In turn, the Spartan 6 is connected to some external SRAM. I need to production test the SRAM. As I see it, I have two options: - Write an SRAM driver directly from the FPGA (without involving the Cortex). - Route the Cortex memory pins through the FPGA to the memory. Reading through the specs of the SRAM, it seems that writing an SRAM driver for the FPGA is a relatively difficult task. I am therefore inclined to ...hi,i read in the olimex site that: "When the TST pin is set during power-up and PGMEN0, PGMEN1 and PGMEN2 are set, the device is entering is a specific test mode and performs a SAM-BA? Boot System Recovery which consists in copying the SAM Boot Assistant (SAM-BA?) in the first two sectors of the on-chip Flash memory. The system recovery procedure takes 10s." but in datasheet i read that it copy it self in sram amp only 8k bytes left for user. can some one explain it for me?which one is right? thanks.Dear all, Here i have some doubt please help me. I am interfacing 1Mb SRAM to LM3S3748 processor using SPI protocol. For this i used 4 GPIO pin and configured as SPI protocol. I can able to write and read data from memory location of SRAM separately. My doubt is that in LM3S3748 limited in built RAM is there so i cant store all my ...I thought I would see how well SPI SRAM works when shared. The Mini is writing to the SRAM and the Panda is reading it to display. There is no direct communication so they just wait for the CS line to be free before using it. The gates are slow at 3V so the max speed would be 3Mhz and it's stable at 2Mhz.Has anyone used the 'DA210 with external SRAM to get a VGA display resolution? The datasheet says only WQVGA is supported with the internal 96k RAM. So to use a bigger display an external SRAM is required. I only need a limited number of colours, say 16, and no fast moving graphics. Even with an external SRAM, the 'DA210 is cheaper than a more 'traditional solution'. I have no love for the products of Solomon or Epson - sorry to anyone reading who works for those companies.I'm using the Keil MCBSTM32F400 development board and I'd like to start using the external SRAM. From the user's guide the SRAM uses the following pins and is at the following location: SRAM FSMC_NE3 / PG10 0x68000000 - 0x681FFFFF I'm having trouble accessing the memory. When trying to write, nothing happens and when reading back I always get 0xFF. Does anyone have an example of setting up the FSMC for the Keil development board to use its external SRAM? Is there a Keil example application that shows how to use the memory? What I've tried so far: In the standard system_stm32f4xx.c ...For our prototypes we used STMicroelectronics SRAM 4Mbit, 512Kx8, 55ns (M68AW511AL). Now it is getting near production I find that they have stopped making that memory. Lots of other companies make equivalent SRAM, but can I assume it is going to work ok? Our application requires an access time of 60ns to the SRAM, so within the SRAM spec. In an ideal world I'd get one of the new types and prototype with it before ordering, but lead times are so long at the moment. So I want to place an order (1000 units) for our production run asap. Is that a bad idea? Thanks, JimHi guys! I have one (maybe stupid) question. Is it possible to connect to atmega 128 external 128kb sram memory? Can I use not all address lines(in that case I could address only 60k but still use 128k sram module)? Problem is that it's quite hard to find (I couldn't find) in Lithuania 3,3V external SRAM chips and the only one I have is 128kHi all! What's the difference in "gates density" between a typical CPU L1 cache and on chip static RAM? I mean.. how many logic gates are necessary for e.g. 4 KB of 80486-style L1 cache, and how many for embedded SRAM? I guess that for the latter it's no less than 65536 gates (please feel free to provide an exact value!), but for the L1 cache of equivalent size, how many gates are necessary? (with gates I mean basic NAND gates). Thank you! MikeHi I have one query related microcontroller interface with external memory SRAM that how it detect my previous data stored in memory is currupted and give me error warn anybody suggest any solution for this???